(1) Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly to a method for forming a multi-level wiring structure, a method for forming an insulating film, and a method for forming a surface protective film of a semiconductor device.
(2) Description of the Related Art
Conventional multi-level wiring structures of the type to which the present invention relates are formed, for example, by a method as disclosed in Japanese Patent Application KOKAI (Laid-open) No. Sho 64(1989)-47053. Such conventional method follows the procedure explained hereunder.
As shown in FIG. 1A, a first level wiring 102 of an Al--Si alloy is formed on a semiconductor substrate 101. Then, as shown in FIG. 1B, a first insulating film 103 of phosphosilicate glass (hereinafter referred to as "PSG") is formed over the entire surface by an atmospheric-pressure CVD (Chemical Vapor Deposition) process to a thickness of about 200 nm. Subsequently a glass solution is applied by spinning at a 5000 rpm, and baked at 150.degree. C. for one minute and at 300.degree. C. for thirty minutes to solidify. This procedure for application of the glass solution by spinning and baking is repeated two or three times to form a glass coating film 104 having a thickness of about 200 nm on the wirings 102 as shown in FIG. 1C. Thereafter, the overall glass coating film 104 is etched in a depth of 200 nm by a reactive ion etching (RIE) method to produce a structure as shown in FIG. 1D. Then, the second insulating film 105 of PSG is formed over the entire surface to a thickness of 400 nm by the atmospheric-pressure CVD process, as shown in FIG. 1E. Subsequently, a hole 106 is formed as shown in FIG. 1F, and then a second level wiring 107 is formed to fabricate a two-level wiring structure as shown in FIG. 1G.
However, the conventional or prior art method for forming the multi-level wiring structure as described above has the following problems. That is, in the overall etching step after the formation of the glass coating film, the glass coating film is apt to be over-etched resulting in a considerable deterioration of the surface flatness because the glass coating film has a higher etching rate than that of the PSG film formed by the CVD process.
Moreover, a profile of the formed glass coating film is largely dependent upon an underlying pattern in a manner that a thicker glass coating film is formed on a wider pattern wiring. The glass coating film on the wider pattern wiring remains even after the glass coating film on a thinner pattern wiring has been etched out. Thereafter, upon the formation of the second level wiring after through-holes have been formed, the water content or the moisture hydroscopically contained in the glass coating film is released to oxidize the bottom of the hole, i.e., the surface of the lower level wiring, which oxidation will adversely affect electrical conduction.
These disadvantages result in markedly lowering the yield of production of semiconductor devices and the reliability.
In the formation of insulating films which is a process preceding the formation of the multi-level wiring structure, generally thermal treatment has been widely used. For example, after a silicon oxide film has been formed on a silicon substrate by a thermal chemical vapor deposition process at a temperature of at least 300.degree. C., it is heat-treated at a temperature of at least 900.degree. C. in order to reduce the water content of the film and to make it dense. Moreover, this heat-treatment simultaneously improves the quality of the insulating films which are used as insulating films for semiconductor devices.
However, the conventional process for the forming of the insulating films as described above has disadvantages as follows. When the films are formed by the thermal chemical vapor deposition process at a temperature of about 300.degree. C., they themselves are of a rough texture and have a high water content, and tend to absorb moisture so that they are unsuitable for ready practical use. Therefore, they require a heat-treatment for densification at a temperature of at least 900.degree. C. The temperature of 900.degree. C. or more is undesirable for the production of semiconductor devices. That is, impurities injected into a device region are redistributed by this heat-treatment to make it impossible to achieve desired device properties. Thus, the resultant devices will not be useful for ULSI such as 64 Mbit DRAM and the like to come in the future.
Conventional surface protective films of the type which the present invention concerns are formed by the following process. That is, on a MOS type transistor memory cell having an N.sup.+ -type source 202, an N.sup.+ -type drain 203, a field insulating film (SiO.sub.2) 204, a polycrystalline silicon (Si) gate 205, a storage capacitor electrode 206 composed of polycrystalline Si, a P0S film 207, aluminum electrode wirings 208a and 208b formed on a semiconductor substrate 201 of P-type silicon and the like, as shown in FIG. 2, there is grown a first level silicon oxide film 209 having a thickness of about 100 nm by a plasma-assisted or enhanced CVD process with monosilane (SiH.sub.4) and nitrogen monoxide (N.sub.2 O) at a temperature of about 300.degree. to 400.degree. C. Then, a second level silicon nitride film 210 having a thickness of about 500 nm by the plasma-enhanced CVD process with monosilane (SiH.sub.4) and ammonia (NH.sub.3) at a temperature of about 300.degree. to 400.degree. C.
The prior art method for forming the surface protective films has the following problems. That is, in a region where a plurality of aluminum electrode wirings 308 are disposed closely to one another as diagrammatically shown in FIG. 3, as the aluminum electrode wirings have been required to be made thinner, a protective film 311 (which refers to the silicon oxide film 209 and the silicon nitride film 210 as a whole, which are shown in FIG. 2) formed by the CVD process has inevitably overhangs as shown in FIG. 3 owing to a rigorous irregularity of the surface of the substrate having the aluminum wirings before the protective film 311 is formed by the CVD process. Therefore, when the semiconductor chip is sealed with resin, a thermal stress imposed by the sealing resin may cause breakdown of the aluminum electrode wirings and cracking of the protective film.
Moreover, the formation of the protective film over the aluminum electrode wirings at a temperature not less than 300.degree. C. causes development of hillocks on the surfaces of the aluminum electrode wirings resulting in a lower yield of semiconductor devices to be produced and a great reduction in reliability.
In addition, when the semiconductor devices are continuously operated in a high temperature environment, the thermal stress imposed on the protective film accelerates the breakdown of the aluminum electrode wirings, or corrosion of the aluminum electrode wirings occurs due to the ingress of moisture into the cracks produced in the protective films with a great reduction in reliability, rendering the semiconductor devices to be of no practical use.